| PART |
Description |
Maker |
| 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV |
CLP SINE LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74F113PC 74F113SC 74F113SJ 74F113 74F113SCX |
Dual JK Negative Edge-Triggered Flip-Flop F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| KS74AHCT112 |
Dual J-K Negative-Edge-Triggered Flip-Flops
|
Samsung
|
| SN54LS112A SN54LS112J 74LS112 SN74LS112N SN74LS112 |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
MOTOROLA[Motorola Inc]
|
| SN74LS112D |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
Motorola, Inc
|
| SN74LS114D SN54LS114J SN74LS114N SN54LS114A SN5474 |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
MOTOROLA[Motorola Inc]
|
| 74HC112 74HCT112 74HC112N 74HC112D 74HC112DB 74HCT |
Dual JK flip-flop with set and reset; negative-edge trigger
|
PHILIPS[Philips Semiconductors]
NXP Semiconductors
|
| 74F114PC |
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
|
Fairchild Semiconductor
|
| MAX768 MAX768EEE MAX768C_D MAX768C/D |
Low-Noise, Dual-Output, Regulated Charge Pump for GaAsFET, LCD, and VCO Supplies
Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CFP -55 to 125
|
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
Maxim Integrated Products, Inc.
|
| 74LCX112 74LCX112M 74LCX112MTC 74LCX112SJ 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
|
FAIRCHILD[Fairchild Semiconductor]
|
| CD74HCT73E |
<font color=red>[Old version datasheet]</font> Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
TI store
|
